Signal detection circuit

ABSTRACT

A readout signal is channeled through two paths, one for identifying signal peaks, the other for sensing slope and net change of signal voltage or pulse amplitude. A gate generator allows reading a pulse only when slope sense and amplitude change are acceptable and coincident with a detected signal peak.

United States Patent Inventors [an H. Graham; [56] Relerences CitedHarry A. Skovmand; Jack S. Swartz, all of UNlTED STATES PATENTS A 1 No m3,048,717 8/1962 Jenkins 328/114 PP- Q 4 833 4168 'ti tl Filed J 1970 3,37, 9 Razai se a 328/114X Patented Dec. 28, 1971 Primary Examiner-DonaldD. Fen-er Assignee International Bu in Mgchines Assistant Examiner-B. P.Davis Corporation Attorney-Sughrue, Rothwell, Mion, Zinn & MacpeakAnnouk,N.Y.

ABSTRACT: A readout signal is channeled through two SIGNAL DETECTIONCIRCUIT paths, one for identifying signal peaks, the other for sensing10 Claims, 9Drawlilg Figs. slope and net change of signal voltage orpulse amplitude. A (I 307 2 l gate generator allows reading a pulse onlywhen slope sense I 3 and amplitude change are acceptable and coincidentwith a 307/235 328/1 15 detected signal peak. Int. (I 1103K 17/00 Fieldof Search 328/ l 14, 115,14 G; 307/231, 235

P 2 LINEAR (1D 3? (D (E) READOUT DETECTOR DELAY AND DATA OUTPUT SIGNAL11 GATE GEN.

PATENTEU 05228 197i SHEET 1 OF 4 T U P T U 0 m A D ET m G I A F M L E D5 1 m Tl E N m Mr! E 6 0 T 3 w R L O A A M W IIEI LRS 70 S S R 3 O a I F0 0 N N A A 7 70 1 2 S S S 70 3 H L l A I. 5 I; VI m m. v v D D On 2 mmam M FE E U E DIAL rr 9 R W E NA H DATA INVENTORS IAN H. GRAHAM HARRYA. SKOVMAND JACK S. SWARTZ ATTORNEYS PATENTED BEC28 I97! SHEET 3 I]? 4(m H H H mm H n n n H j J j j DATAOUT J=Ho[e+e'] LINEAR AMP a d/mDETECTOR DELAY AND ED FILTER WA 73 R-C LDETECTOR LATCH AND GATE OR GENDETECTOR im 74 71 I SIGNAL DETECTION CIRCUIT BACKGROUND OF THE INVENTIONl. Field of the Invention This invention relates to a novel and improvedsignal detection circuit, and in particular to a high density datareadout system.

2. Description of the Prior Art The trend in the technology of recordingsystems is to record data with higher and higher densities and closelypacked data pulses to utilize the available storage surface in anoptimum manner. Apparently, as packing densities are in creased, thereare attendant problems, such as pulse crowding, with resultant reductionin signal amplitude of adjacent bits, asymmetry of the pulses, bitshift, and the like. Thus, during the readback process, low amplitudenoise signals, sloping shoulder portions between data bits, and otherspurious nondata voltages, may be detected and interpreted erroneouslyas data; or valid data may be distorted or lost.

SUMMARY OF THE INVENTION An object of this invention is to provide amore reliable signal detection circuit, wherein transients and noisesignals are eliminated from the readback output signal.

Another object of this invention is to provide a signal detectoroperable with high density data, wherein noise and signal overshoot areeasily separated from the valid data.

According to this invention, readout data is passed to an output orutilization device only if four prescribed conditions are met by eachdata bit or pulse; namely, (1) a minimum leading positive, or negative,slope; (2) a zero slope peak; (3) a minimum negative, or positive,slope; and (4) a minimum amplitude. To sense each pulse for theseconditions, the readout circuit has two signal channels including, interalia, a peak detector, a slope detector, and a circuit designated as aAV detector which senses the net change of amplitude of the linearreadout signal after each peak. To obtain a valid data pulse, the peakdetected signal is delayed and applied to a logic AND circuit with agating pulse developed by the AV de- ICCIOI'.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described ingreater detail with reference to the drawing in which:

FIG. I is a block circuit diagram depicting the basic concept of thisinvention.

FIG. 2 is a timing diagram of the signals produced with the circuit ofFIG. 1.

FIG. 3 is a block diagram of the inventive circuit in greater detail.

FIG. 4 is a block diagram of the FM slope detector, used in the circuitof FIG. 3.

FIG. 5 is a schematic circuit diagram of a AV detector as used in thecircuit of FIG. 3.

FIG. 6 is a schematic diagram of the gate generator, found in FIG. 3.

FIG. 7 is a series of waveforms applicable to the circuit of FIG. 6.

FIG. 8 is a block diagram of an alternate circuit embodying theinventive concept of the present application.

FIG. 9 is a schematic circuit diagram of a portion of FIG. 8.

DETAILED DESCRIPTION OF THE DRAWINGS In accordance with the basicconcept of the present invention, and as illustrated by the blockdiagram in FIG. I and the waveforms of FIG. 2, a linear signal such asthat shown at A in FIG. 2 represents a raw readout signal and is appliedto a pair of detection channels 5 and 7 at input terminal 3. Bothchannels 5 and 7 are connected at their output sides to an AND gatecircuit means 9 whose output at output terminal 11 represents the dataoutput. Channel 5 includes a peak detector I3 which may be aconventional peak detector of the type used in readout systems fordouble-frequency-type recording. The output from peak detector 13,illustrated by waveform B in FIG. 2, is connected to and delayed bydelay means 17 and then applied to the AND-gate 9. Delay means 17operates to align the peak detector output pulses with the gatingpulses, to be described hereafter, generated by channel 7.

Channel 7 includes a gate generator 15 which operates to provide gatingoutput pulses in response to the slopes in the raw readback signalmeeting predetermined requirements set by circuitry included in thegating generator I5. Basically, the requirements are that the slope musthave at least a minimum amplitude and must be of opposite sense to thepreviously detected slope also having at least said minimum amplitude.The gating pulses produced by gate generator 15 are shown in waveform Cof FIG. 2. Since the criteria for generating a gating pulse depends inpart on the slope trailing the peak, the gating pulse necessarily occursafter the peak pulse output. Consequently, delay means 17 is needed toproperly align the pulses from the peak detector 13 with the gatingpulses from gate generator 15.

In the more detailed block diagram shown in FIG. 3, the readout coil 1is connected to a linear amplifier 18 which provides two outputsrepresenting respectively the raw readout signal at 0 phase and the rawreadout signal at 180 phase. The opposite phase signals are used toenable the detection circuitry, which is duplicated for each of the twophase waveforms, to detect only the positive peaks in both waveforms. Itwill be noted'that the positive peaks in the phase reversed raw readoutsignal correspond to the negative peaks in the nonphase reversed rawreadout signal. The 0 and 180 signals are applied to a peak detector 21which is illustrated in more detail in FIG. 4 and which comprises adifierentiator 47, overdriven amplifiers 49, detectors 51, and outputdriver amplifiers 53. The differentiators 47 produce base linecrossovers for each positive peak of the input signals and drive theoverdriven amplifiers 49 which may be several DC coupled amplifiers. Theamplifiers 49 overdrive and clip the input signals thereto producing aseries of square waves of different lengths equal to the spacing betweensignal peaks. The square waves are applied to detectors SI which produceoutput pulses, one for each positive leading edge of the pulses appliedthereto. The latter pulses are amplified by the output driver amplifier53 and applied as the output of peak detector 21 to the delay circuits23 and 25.

The 0 and l readout signals are applied to a filter 27 which operates toincrease the slope of all trailing edge slopes in the signals appliedthereto. The filtered signals are then applied to a pair of identicalvoltage difference detection circuits 29 and 31. Circuits 29 and 31 eachoperate to compare the slope amplitude of the trailing slopes appliedthereto with a predetermined minimum amplitude and provide an outputtriggering signal to a latch 33. The latch 33 operates in a conventionalmanner in response to the pulses applied from voltage differencedetectors 29 and 31. The two latch outputs are fed back to the circuits29 and 31 respectively for aiding in clamping the input signals theretoin a manner which will be described in more detail in connection withFIG. 5. The purpose of latch 33 is to ensure that a gating pulse willnot be generated unless the present slope, which meets the requirementsof one of the circuits 29 and 31, is of opposite sense to the priordetected slope. For example, a positive slope in the raw readout signalmeeting the minimum voltage requirements will result in an outputtriggering pulse from circuit 31. The latter output triggering pulsewill reset latch 33, thereby triggering the single shot circuit 37whichgenerates the gating pulse. If the next slope which satisfies theminimum amplitude requirement is also a positive slope, therebyresulting in another output triggering pulse from circuit 31, the latch33, already being in the reset state, will not be affected, andtherefore no gating pulse will be generated. However, if the slope is anegative slope, the output triggering pulse will appear at the output ofcircuit 29 thereby resetting the latch and initiating the single shotcircuit 35 to generate a gating pulse. Single shot circuits 35 and 36generate gating pulses which are connected respectively to a pair ofAND-gates 39 and 41 which are also connected respectively to the outputsof delay means 23 and 25. The peak pulses passing through delay means 23and 25 and gated through AND-gates 39 and 41 respectively are appliedthrough an OR-circuit 43 to a single shot circuit 45 whose output pulsesare of a standard width and represent the data contained in the rawreadout signal. In FIG. 3, the lead lag filter 27, voltage detectioncircuits 29 and 31, latch 33, and single shot circuits 35 and 37correspond to the gate generator of FIG. 1.

An example of one circuit for use as the voltage difference detectors 29and 31, (both being identical) is illustrated in FIG. 5. The linearfiltered signal from one of the lead lag filters 27 of FIG. 3 is appliedto input tenninal 300 of the voltage difference detector and an outputpulse appears at output terminal 328 in response to a trailing slopehaving a voltage magnitude greater than a reference difference voltageAV. The feedback from the latch 33, shown in FIG. 3, is connected to atransistor 306 via wire 308. The transistor 306 is conducting during theearly portion of the positive going slope of the input signal and aidsin clamping all positive peaks to a reference value V,;.

The linear input signal from the lead lag filter is applied to anemitter-follower transistor 301. The emitter of transistor 301 isconnected in series with diode 303 and resistance 305. The diode 303 isincluded in the circuit to prevent emitter base breakdown during thetime when the clamping transistor 306 is conducting. The waveform at thejunction of diode 303 and resistance 305 is applied to a chargingcapacitor 316 via a filter comprising capacitor 302 and resistance 304.The values of capacitor 302 and resistance 304 are chosen to permit acertain range of slope change to be applied to the capacitor 316. Anygreater or lesser slope will be reduced by the RC time constants. Thediode 310 operates as a clamping diode in conjunction with transistor306 to clamp each positive peak to the reference potential V applied toterminal 312. In operation, during the positive going slope, the chargeon capacitor 316 builds up to the positive peak but is clamped at V,,.The conduction of transistor 306 during the initial part of the positivegoing slope assists in setting each positive peak at exactly -V R plus adiode voltage drop for diode 310. Following the positive peak, thevoltage across the capacitor decays from the positive peak reference ofV,, by discharging through resistance 314. The voltage across capacitor316 is connected to the base terminal of transistor 322 which isnormally conducting. The transistors 322 and 324 are differentiallyconnected to provide an output pulse at the collector of transistor 322when the voltage across capacitor 316 drops below the voltage applied tothe base of transistor 324. The difference between the peak voltage oncapacitor 316 (V,;) and the voltage on the base of transistor 324 is thereference voltage difference. Thus, if the negative going slope of theinput waveform has a slope magnitude greater than AV, an output pulsewill be produced.

The reference voltage difference AV is created by applying a voltage Vto a terminal 321 which is connected through a resistance 317 to thejoined emitters of transistors 322 and 324. Terminal 321 is alsoconnected through a potentiometer 318, having wiper arm 320, to theterminal 312. The wiper arm 320 is connected to the base of transistor324. It should be noted that V is more negative than V and thus thevoltage applied to the base of transistor 324 is more negative than Vand transistor 324 will be cut off at the positive peaks of the inputwaveform. The difference between V,, and the voltage on the base oftransistor 324 is AV. Thus, when the voltage on capacitor 316 drops fromV, an amount greater than AV, transistor 322 will be cut off resultingin the positive going output pulse. An identical circuit to onedescribed receives the linear signal phase reversed and thereforeprovides output pulses in response to slope trailing the opposite peaks.The output terminals from the two identical circuits are connectedrespectivelyto the reset and set inputs of the latch 33 of FIG. 3.

An alternative circuit for the gate generator means of FIG. 3 isillustrated in FIG. 6. The circuit of FIG. 6, when used in the blockdiagram embodiment of FIG. 3, would have its two input terminalsconnected to the output of linear amplifier 19 and its two outputterminals connected respectively to the gating inputs of AND-gates 39and 41. The waveforms shown in FIG. 7 and identified by A, B, C, D, E,F, and G represent the waveforms as they appear in the circuit of FIG. 6at points identified by corresponding letters. Waveforms H and .Irepresent respectively the delayed pulses which are detected by the peakdetector and the latter pulses which are gated through the AND gates bythe gating pulses.

The raw readout signal at 0 phase is applied at input terminal 2 and theraw readout signal at phase is applied at input terminal 4. Thecircuitry which operates upon the signal applied at input terminal 4 isidentical to the circuitry which operates upon the signal applied atterminal 2. Both circuits detect the positive going slope AV following anegative peak of the respective input signals. The values of theresistances and capacitances shown in FIG. 6 represent only one specificexample of values which may be used in the circuit.

In contrast to the circuit described above and illustrated in FIG. 5,the circuit of FIG. 6 operates to clamp the negative peaks at areference voltage and to detect the AV of the positive going slopes.Considering the linear signal applied at input terminal 2, the waveformappearing at the base terminal of transistor 12 has its negative peaksclamped or referenced to a reference potential of 3 volts shown in theexample. The clamping action is provided by diode 11 with the assistanceof transistor 16. The AV reference is set by the potential at the baseof transistor 14 which is controlled by a 2K potentiometer. The outputpulses generated in response to a detected slope appear at the collectorof transistor 12 as negative going pulses. For the signal applied atinput terminal 4, the output pulses appear at the collector oftransistor 10 and are also negative going pulses. It can be seen thatthe clamping of the negative peaks of the input signal at terminal 4 asit appears at the base of transistor 10 are clamped to the samereference value, 3 volts, by diode 13 with the assistance of transistor18. Also, the reference level set by transistor 14 and associatedcircuitry controls the conduction of transistor 10 as well as transistor12.

In operation, as a negative going slope appears at input terminal 2 itwill be clamped at 3 volts due to the conduction of diode 1 1. Theclamping action is assisted by the conduction of transistor 16 throughtransistors 20 and 22. It can be seen that transistor 16 will beconducting during the negative going slope at input terminal 2 becausethe base of transistor 16 is connected to input terminal 4 which willsimultaneously be receiving a positive going slope. Consequently, whenthe negative peak of the input signal at terminal 2 is reached, thevoltage at the base of transistor 12 will be at the negative referencevoltage of 3 volts (plus the forward drop of diode 11). As the inputslope goes positive, diode 11 cuts off and transistor 16 also cuts off.The slope rises from the 3-volt reference level by an amount determinedby the slope rise at the input terminal 2. If the rise goes above thereference potential appearing at the base of transistor 14, thetransistor 12 will be rendered conductive, cutting off transistor 14,and resulting in a negative going output pulse at the collector oftransistor 12. Output pulses are created at the collector of transistor10 in an identical manner.

Assuming that input terminal 2 receives the signal at 0 phase and inputterminal 4 receives the signal at 180 phase the negative going pulses atthe collector of transistor 12 represent negative peaks satisfying theslope voltage difference requirement whereas the pulses appearing at thecollector of transistor 10 represent positive peaks satisfying the sloperequirement. The positive peak and negative peak pulses are applied tothe set and reset inputs of a latch which comprises the interconnectedAND-invert gates 24 and 26. Assuming that the last slope satisfying thevoltage difference requirement was a trailing slope of a positive peak,the potential at the output of gate 26 will be high and the potential atthe output of gate 24 will be low. If the next triggering pulse alsoappears at the collector of terminal 10, it will have no affect on thelatch. However, if the next triggering pulse appears at the collector ofterminal 12, it will cause the latch to switch states. The output ofgate 24 will rise in potential causing the output of gate 26 to go lowin potential. The low potential at the output of gate 26 holds the latchin this condition until a subsequent triggering pulse at the collectorof transistor is received. The negative going potential at the output ofgate 26 is applied through the 68 picofarad capacitor to the baseterminal of a transistor 30. The transistor 30 is normally conductingbut is cut off by the negative potential applied to the base thereof.When the transistor is cut off, the collector thereof rises creating apositive going gating pulse representing the detection of a slopefollowing a negative peak which satisfies the slope magnituderequirement. It will be noted that, due to the action of the68-picofarad capacitor and the 5.1K resistance connected to the base oftransistor 30, the output pulse only lasts for a short period of timeeven though the output of gate 26 remains at the low potential until asubsequent triggering pulse is received. The transistor 28 which isconnected via a 63-picofarad capacitor to the output terminal of thegate 24 operates in the same manner as transistor 30. The output gatingpulses appearing on the collector of transistor 28 represent negativegoing slopes of the original raw readout signal which satisfy the AVrequirements.

An alternative embodiment to the one shown in FIG. 3 is i] lustrated bythe block diagram of FIG. 8. The primary difference between the blockdiagram of FIG. 8 and that of FIG. 3 is that in FIG. 8 the slopecriteria is measured by detecting the amplitude of the readout signalafter it is differentiated. In the differentiated signal the amplitudeof the peaks represents the degree of the slope. In order to generate agating output, the peaks of the differentiated signal must be above aminimum amplitude which is equal to the average of the differentiatedsignal, and each peak must have an amplitude above a percentage of thepreceding peak. A first positive peak, representing the occurrence of apositive slope, is stored on a capacitor which is then allowed todischarge. With time, the voltage on the capacitor decays. Thesucceeding positive peak, representing the succeeding positive slope, iscompared with the voltage on the capacitor. Thus, the closer a peak of adifferentiated signal is to a prior peak of the same signal waveform,the higher its amplitude must be in order to result in the generation ofa gating output pulse. Since the peak amplitude of the differentiatedsignal represents slope steepness and since the time between peaks is anindication of slope duration, a differentiated signal which satisfiesthe above-mentioned criteria represents a slope having sufficientmagnitude AV to be recognized as a data bit.

In FIG. 8, the differentiator 47 corresponds to the differentiator ofFIG. 4 and the detector 51 corresponds to the detector of FIG. 4. Theoverdrive amplifiers 49 and output driver amplifiers 53 of FIG. 4 arepreferably included in FIG. 8 but are not shown therein. Also, it willbe noted that in FIG. 8 the outputs of the detector 51 are combined toprovide a single output which is delayed by a single delay means 23 andconnected to a single AND-gate 61. Also, the gating pulses which aregenerated by the slope detecting circuitry are connected to an OR-gate73 whose output, in turn, is connected to a gate generator 74 which maybe a single shot corresponding to single shot 45 of FIG. 3. It will beapparent that the delay means 23 and AND-gate 61 of FIG. 8 may bereplaced by a pair of delay means and a pair of AND gates such as thatused in FIG. 3, or in the alternative may be substituted for the pair ofdelay means and the pair of AND gates used in FIG. 3.

The differentiator 47 forms a part of the peak detecting channel and theslope detecting channel in the embodiment of FIG. 8. It will also beapparent that each channel may have its own individual ditferentiatorcircuit. The differentiator waveforms, representing respectively the 0phase readout signal differentiated and the 180 phase readout signaldifferentiated are applied to a pair of RC detector circuits 63 and 65.The RC detector circuits operate to provide an output pulse if the inputpeak is above a preset minimum and above a percentage of the previouspeak as explained above. The output pulses from the RC detector circuitsare applied to a latch 67 and also to AND-gates 69 and 71. The latch 67in combination with AND-gates 69 and 71 operates to ensure that a gatingpulse is not generated unless a pulse output from either one of the RCdetector circuits is preceded by a pulse output from the other RCdetector circuit. The circuit of FIG. 8 illustrated by blocks 63, 65,67, 69, 71, 73, 74, and 61 is illustrated in schematic form in FIG. 9.

The 0 phase and phase signals after being differentiated by thedifferentiator 47 of FIG. 8 are applied respectively to terminals 200and 201. The circuitry of the 0 phase channel including transistors 202,204, 206, 208, 210, 212, and 214 is identical to the circuitry in the180 phase channel including transistors 203, 205, 207, 209, 211, 213,and 215. Therefore, only the 0 phase channel will be described in anydetail. The input signal is applied to an emitter follower 202 whoseoutput is applied to a filter and also to the base of transistor 206.The filter, including the l .2K resistor and the 0.1-microfaradcapacitor, serves to provide a voltage at the base of transistor 204representing the average of the differentiated input signal. When theinput signal rises above the average amplitude, transistor 206 conductsand charges the 300-picofarad storage capacitor to the peak value. Asthe peak drops off, the 300-picofarad storage capacitor dischargesthrough the 1.3K resistor. Each time the input signal rises above thevoltage on the storage capacitor, transistor 206 will conduct. Thus, apositive going output pulse at the collector of transistor 206 is anindication that a peak of the differentiated signal (corresponding to aslope of the readout signal) has met the requirements of duration andamplitude set by the averaging circuit and the storage capacitorcircuit. The positive going output pulse from the collector oftransistor 206 is shaped and amplified by an amplifier circuit includingtransistors 208 and 210 and applied as a negative going pulse to acircuit which includes transistors 212 and 214. The circuit includingtransistors 212 and 214 provides two outputsa positive going output atthe collector of transistor 212 and a negative going output pulse at thecollector of transistor 214. Similar outputs corresponding to oppositesense slopes detected by the corresponding circuitry appear at thecollector of transistor 213 and the collector of transistor 215. Thenegative going pulse from the collector of transistor 214 operates toset a latch, corresponding to latch 67 of FIG. 8, which comprises a pairof cross-connected AND- invert circuits. One of the AND-invert circuitsincludes diodes 216 and 218, and transistors 220 and 222. The otherAND-invert circuit includes diodes 217 and 219, and transistors 221 and223. The latch is set by a negative going pulse at the cathode of diode216 and is reset by a negative going pulse at the cathode of diode 217.When in the set condition, the upper output of the latch, taken at thecollector of transistor 222, is a high level voltage whereas the loweroutput of the latch taken from the collector of transistor 223 is a lowlevel voltage. When in the reset condition, the voltage levels of thetwo outputs are reversed.

The circuit including diodes 224 and 226 corresponds to the AND-gate 69of FIG. 8, and the circuit including diodes 225 and 227 corresponds tothe AND-gate 71 of FIG. 8. Assuming that a slope of opposite sense waspreviously detected, and thereby the latch is in the reset condition,the cathode of diode 225 will be at a high level voltage. The occurrenceof a positive going pulse at the collector of transistor 212 raises thecathode of diode 227 to a high level voltage thereby resulting in anoutput from the AND gate which includes diodes 225 and 227. The lattercondition triggers a gate pulse generating circuit which includestransistors 228, 230, and 232. A positive going gating pulse from thelatter circuit is applied as one input to an AND gate, the other inputcoming from the delay means 23. The latter mentioned AND gate includesthe circuitry of transistors 240, 242, 244, and 246, and operates toWhat we claim is: l. A readout circuit for detecting high density signaldata in a raw readout signal comprising:

a. peak detecting channel means for detecting peaks in said raw readoutsignal and providing output indicating said peaks,

b. slope detecting channel means for detecting slopes in said rawreadout signal meeting preset slope sense and amplitude requirements andproviding a gating pulse for each detected slope, said slope detectingchannel means including means for clamping selected peaks in said rawreadout signal to provide a reference level against which slopeamplitudes are measured, and

c. gating means connected to said peak detecting and slope detectingchannel means responsive to each gating pulse representing a givendetected slope of said raw readout signal for passing to an outputterminal the peak detector output resulting from detection of the peakof said detected slope.

2. A readout circuit for detecting high density signal data comprising:

a. first and second signal channels for receiving a raw readout signal,

b. said first channel including means for detecting those portions ofthe readout signal having peaks greater than a predetermined amplitude,and means for delaying such detected signal portions,

c. said second channel including means for detecting only those signalportions having slopes of opposite phase than the previously detectedslopes and which are greater than a predetermined slope and duration,and

d. gating means at the output of said first channel for passing onlythose signals that have the proper slope sense and pulse amplitude, andwhich are coincident with the detected signal peaks.

3. A readout circuit for detecting high density signal data in a rawreadout signal comprising:

a. peak detecting channel means for detecting peaks in said raw readoutsignal and providing output indicating said peaks,

b. slope detecting channel means for detecting slopes in said rawreadout signal meeting preset slope sense and amplitude requirements andproviding a gating pulse for each detected slope, and

c. gating means connected to said peak detecting and slope detectingchannel means responsive to each gating pulse representing a givendetected slope of said raw readout signal for passing to an outputterminal the peak detector output resulting from detection of the peakofsaid detected slope,

wherein said slope detector channel means comprises:

slope amplitude detecting means for detecting slope voltage changegreater than a preset minimum,

slope sense memory means connected to said slope amplitude detectionmeans for storing an indication of the sense of the last slope detectedto said slope amplitude detecting means, and

gate generating means for generating said gating pulse in response tothe detection of a slope amplitude from said slope amplitude detectingmeans wherein said detected slope has a sense opposite to the senseindicated by and stored in said slope sense memory.

4. The readout circuit as claimed in claim 3 wherein said slope detectorchannel means comprises:

said readout signal having a voltage change from a negative peak greaterthan a predetermined amount,

b. second means for generating an output pulse on a second outputterminal in response to each negative going slope 5 of said readoutsignal having a voltage change from goin slope posltlve peak greaterthan said predetermine amount, and

c. logic means connected to said first and second output terminals forgenerating a gating pulse in response to each said output pulse providedthe preceding said output pulse appeared on the opposite outputterminal.

5. The readout circuit as claimed in claim 3 wherein said peak detectingchannel means comprises a peak detector means for providing peak outputpulses and a delay means connected to said peak detector output fordelaying said peak output pulses.

6. The readout circuit as claimed in claim 5 wherein said slope detectorchannel means comprises:

a. slope amplitude detecting means for detecting slope voltage changegreater than a preset minimum,

b. slope sense memory means connected to said slope amplitude detectionmeans for storing an indication of the sense of the last slope detectedby said slope amplitude detecting means, and

. gate generating means for generating said gating pulse in response tothe detection of a slope amplitude from said slope amplitude detectingmeans wherein said detected slope has a sense opposite to the senseindicated by and stored in said slope sense memory. I

7. The readout circuit as claimed in claim 5 wherein said slope detectorchannel means comprises:

a. first means for generating an output pulse on a first output terminalin response to each positive going slope of said readout signal having avoltage change from a negative peak greater than a predetermined amount,

b. second means for generating an output pulse on a second outputterminal in response to each negative going slope of said readout signalhaving a voltage change from a positive peak greater than saidpredetermined amount, and

c. logic means connected to said first and second output terminals forgenerating a gating pulse in response to each said output pulse providedthe preceding said output pulse appeared on the opposite outputterminal.

8. The readout circuit as claimed in claim 7 wherein said first andsecond means are identical and one of said first and second meansreceives said raw readout signal and the other of said first andsecondmeans receives said raw readout signal phase reversed.

9. The readout circuit as claimed in claim 8 wherein said first meanscomprises:

a. clamping means for clamping all negative peaks of the signal appliedthereto to a reference potential,

b. means connecting said raw readout signal to said clamping means, and

c. comparison means connected to said clamping means for providing anoutput pulse when said clamped signal rises above said reference by apredetermined amount.

10. The readout circuit as claimed in claim 8 wherein said first meanscomprises:

a. clamping means for clamping all positive peaks of the signal appliedthereto to a reference potential,

b. means connecting said raw readout signal to said clamping means, and

5 c. comparison means connected to said clamping means for providing anoutput pulse when said clamped signal goes below said reference by apredetermined amount.

t i =8 k 18

1. A readout circuit for detecting high density signal data in a rawreadout signal comprising: a. peak detecting channel means for detectingpeaks in said raw readout signal and providing output indicating saidpeaks, b. slope detecting channel means for detecting slopes in said rawreadout signal meeting preset slope sense and amplitude requirements andproviding a gating pulse for each detected slope, said slope detectingchannel means including means for clamping selected peaks in said rawreadout signal to provide a reference level against which slopeamplitudes are measured, and c. gating means connected to said peakdetecting and slope detecting channel means responsive to each gatingpulse representing a given detected slope of said raw readout signal forpassing To an output terminal the peak detector output resulting fromdetection of the peak of said detected slope.
 2. A readout circuit fordetecting high density signal data comprising: a. first and secondsignal channels for receiving a raw readout signal, b. said firstchannel including means for detecting those portions of the readoutsignal having peaks greater than a predetermined amplitude, and meansfor delaying such detected signal portions, c. said second channelincluding means for detecting only those signal portions having slopesof opposite phase than the previously detected slopes and which aregreater than a predetermined slope and duration, and d. gating means atthe output of said first channel for passing only those signals thathave the proper slope sense and pulse amplitude, and which arecoincident with the detected signal peaks.
 3. A readout circuit fordetecting high density signal data in a raw readout signal comprising:a. peak detecting channel means for detecting peaks in said raw readoutsignal and providing output indicating said peaks, b. slope detectingchannel means for detecting slopes in said raw readout signal meetingpreset slope sense and amplitude requirements and providing a gatingpulse for each detected slope, and c. gating means connected to saidpeak detecting and slope detecting channel means responsive to eachgating pulse representing a given detected slope of said raw readoutsignal for passing to an output terminal the peak detector outputresulting from detection of the peak of said detected slope, whereinsaid slope detector channel means comprises: slope amplitude detectingmeans for detecting slope voltage change greater than a preset minimum,slope sense memory means connected to said slope amplitude detectionmeans for storing an indication of the sense of the last slope detectedto said slope amplitude detecting means, and gate generating means forgenerating said gating pulse in response to the detection of a slopeamplitude from said slope amplitude detecting means wherein saiddetected slope has a sense opposite to the sense indicated by and storedin said slope sense memory.
 4. The readout circuit as claimed in claim 3wherein said slope detector channel means comprises: a. first means forgenerating an output pulse on a first output terminal in response toeach positive going slope of said readout signal having a voltage changefrom a negative peak greater than a predetermined amount, b. secondmeans for generating an output pulse on a second output terminal inresponse to each negative going slope of said readout signal having avoltage change from going slope positive peak greater than saidpredetermined amount, and c. logic means connected to said first andsecond output terminals for generating a gating pulse in response toeach said output pulse provided the preceding said output pulse appearedon the opposite output terminal.
 5. The readout circuit as claimed inclaim 3 wherein said peak detecting channel means comprises a peakdetector means for providing peak output pulses and a delay meansconnected to said peak detector output for delaying said peak outputpulses.
 6. The readout circuit as claimed in claim 5 wherein said slopedetector channel means comprises: a. slope amplitude detecting means fordetecting slope voltage change greater than a preset minimum, b. slopesense memory means connected to said slope amplitude detection means forstoring an indication of the sense of the last slope detected by saidslope amplitude detecting means, and c. gate generating means forgenerating said gating pulse in response to the detection of a slopeamplitude from said slope amplitude detecting means wherein saiddetected slope has a sense opposite to the sense indicated by and storedin said slope sense memory.
 7. The readout circuit as claimed in claim 5wherein said slope detector channel means comprises: a. firSt means forgenerating an output pulse on a first output terminal in response toeach positive going slope of said readout signal having a voltage changefrom a negative peak greater than a predetermined amount, b. secondmeans for generating an output pulse on a second output terminal inresponse to each negative going slope of said readout signal having avoltage change from a positive peak greater than said predeterminedamount, and c. logic means connected to said first and second outputterminals for generating a gating pulse in response to each said outputpulse provided the preceding said output pulse appeared on the oppositeoutput terminal.
 8. The readout circuit as claimed in claim 7 whereinsaid first and second means are identical and one of said first andsecond means receives said raw readout signal and the other of saidfirst and second means receives said raw readout signal phase reversed.9. The readout circuit as claimed in claim 8 wherein said first meanscomprises: a. clamping means for clamping all negative peaks of thesignal applied thereto to a reference potential, b. means connectingsaid raw readout signal to said clamping means, and c. comparison meansconnected to said clamping means for providing an output pulse when saidclamped signal rises above said reference by a predetermined amount. 10.The readout circuit as claimed in claim 8 wherein said first meanscomprises: a. clamping means for clamping all positive peaks of thesignal applied thereto to a reference potential, b. means connectingsaid raw readout signal to said clamping means, and c. comparison meansconnected to said clamping means for providing an output pulse when saidclamped signal goes below said reference by a predetermined amount.